Commit c7aba002 authored by Ralf Stemmer's avatar Ralf Stemmer

First public release

parent 16b0d26b
In MatLab:
[h,g,n,k] = hammgen(6)
1,1,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,1,1,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,0,1,1,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,0,0,1,1,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,0,0,0,1,1,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,1,0,0,0,1,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,0,1,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,1,0,1,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,0,1,0,1,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,1,0,0,1,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,1,1,0,0,1,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,0,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,1,0,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,0,1,0,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,1,0,0,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,0,1,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,1,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,0,1,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,0,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,1,0,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,1,1,0,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,0,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,1,0,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,1,1,0,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,0,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,0,0,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,1,0,0,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,1,1,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1,0,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0
0,1,0,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0
0,0,1,0,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0
1,1,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0
1,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0
0,1,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0
1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0
0,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0
1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0
0,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0
1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0
1,0,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0
1,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0
1,0,0,0,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0
1,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1
#!/usr/bin/env python3
#
# Version: 1.0.0
#
# Changelog:
# 1.0.0 - 09.05.19: First release
#
# Contributors:
# Ralf Stemmer - ralf.stemmer@uni-oldenburg.de
#
import argparse
PARITYCOLUMNS = 6 # Number of parity-columns in the generator matrix
SIGNALLINELIMIT = 5*7 # Limit of signal lines
def column(matrix, i):
return [row[i] for row in matrix]
cli = argparse.ArgumentParser(description="Generate VHDL code for Hamming Encoding")
cli.add_argument("g", type=str, action="store",
help="Path where the Generator Matrix is stored at (CSV encoded).")
args = cli.parse_args()
if __name__ == "__main__":
# 1.: Get data from CSV file
# 1.1 Read Generator Matrix G
with open(args.g) as f:
G = f.read().splitlines()
# 1.2 Separate Parity Matrix P
P = [] # Parity part of the Generator Matrix
for row in G:
columns = row.split(",")[:PARITYCOLUMNS]
P.append(columns)
# 2.: Generate list of inputs for xor operations of each parity bit
# 2.1 Create empty inputs list
inputs = []
for column in P[0]:
inputs.append([])
# 2.2 Fill inputs list with signal numbers
# P[i] = 0 -> no input
# P[i] = 1 -> signal(i) is input
for signal, row in enumerate(P):
# Do not add more signal lines than available for the data to encode
if signal >= SIGNALLINELIMIT:
break
for column, bit in enumerate(row):
if bit == "1":
inputs[column].append(signal)
# 3.: Generate VHDL code
for paritybit, _ in enumerate(P[0]):
print("p%i \033[1;33m<=\033[0m " % (paritybit), end="")
for pos, signr in enumerate(inputs[paritybit]):
if pos > 0:
print(" \033[1;33mxor\033[0m ", end="")
print("counter\033[1;31m(\033[1;35m%i\033[1;31m)\033[0m"%(signr), end="");
print("\033[1;31m;\033[0m")
# vim: tabstop=4 expandtab shiftwidth=4 softtabstop=4
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proc init { cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
set full_sbusif_list [list ]
foreach busif $all_busif {
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
set busif_param_list [list]
set busif_name [get_property NAME $busif]
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
continue
}
foreach tparam $axi_standard_param_list {
lappend busif_param_list "C_${busif_name}_${tparam}"
}
bd::mark_propagate_only $cell_handle $busif_param_list
}
}
}
proc pre_propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
if { $val_on_cell != "" } {
set_property CONFIG.${tparam} $val_on_cell $busif
}
}
}
}
}
proc propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
if { $val_on_cell_intf_pin != "" } {
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
}
}
}
}
}
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TMB_v2_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXIS
C_S00_AXIS_TDATA_WIDTH : integer := 32
);
port (
-- Users to add ports here
start : out std_logic; -- [1:start, 0:stop]
stop : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXIS
s00_axis_aclk : in std_logic;
s00_axis_aresetn : in std_logic;
s00_axis_tready : out std_logic;
s00_axis_tdata : in std_logic_vector(C_S00_AXIS_TDATA_WIDTH-1 downto 0);
s00_axis_tstrb : in std_logic_vector((C_S00_AXIS_TDATA_WIDTH/8)-1 downto 0);
s00_axis_tlast : in std_logic;
s00_axis_tvalid : in std_logic
);
end TMB_v2_0;
architecture arch_imp of TMB_v2_0 is
-- component declaration
component TMB_v2_0_S00_AXIS is
generic (
C_S_AXIS_TDATA_WIDTH : integer := 32
);
port (
start : out std_logic; -- [1:start, 0:stop]
stop : out std_logic;
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic
);
end component TMB_v2_0_S00_AXIS;
begin
-- Instantiation of Axi Bus Interface S00_AXIS
TMB_v2_0_S00_AXIS_inst : TMB_v2_0_S00_AXIS
generic map (
C_S_AXIS_TDATA_WIDTH => C_S00_AXIS_TDATA_WIDTH
)
port map (
start => start,
stop => stop,
S_AXIS_ACLK => s00_axis_aclk,
S_AXIS_ARESETN => s00_axis_aresetn,
S_AXIS_TREADY => s00_axis_tready,
S_AXIS_TDATA => s00_axis_tdata,
S_AXIS_TSTRB => s00_axis_tstrb,
S_AXIS_TLAST => s00_axis_tlast,
S_AXIS_TVALID => s00_axis_tvalid
);
-- Add user logic here
-- User logic ends
end arch_imp;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TMB_v2_0_S00_AXIS is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- AXI4Stream sink: Data Width
C_S_AXIS_TDATA_WIDTH : integer := 32
);
port (
-- Users to add ports here
start : out std_logic; -- [1:start, 0:stop]
stop : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- AXI4Stream sink: Clock
S_AXIS_ACLK : in std_logic;
-- AXI4Stream sink: Reset
S_AXIS_ARESETN : in std_logic;
-- Ready to accept data in
S_AXIS_TREADY : out std_logic;
-- Data in
S_AXIS_TDATA : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
-- Byte qualifier
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
-- Indicates boundary of last packet
S_AXIS_TLAST : in std_logic;
-- Data is in valid
S_AXIS_TVALID : in std_logic
);
end TMB_v2_0_S00_AXIS;
architecture arch_imp of TMB_v2_0_S00_AXIS is
-- function called clogb2 that returns an integer which has the
-- value of the ceiling of the log base 2.
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
begin
if (depth = 0) then
return(0);
else
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if(depth <= 1) then
return(clogb2);
else
depth := depth / 2;
end if;
end loop;
end if;
end;
-- Total number of input data.
constant NUMBER_OF_INPUT_WORDS : integer := 8;
-- bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
constant bit_num : integer := clogb2(NUMBER_OF_INPUT_WORDS-1);
-- Define the states of state machine
-- The control state machine oversees the writing of input streaming data to the FIFO,
-- and outputs the streaming data from the FIFO
type state is ( IDLE, -- This is the initial/idle state
WRITE_FIFO); -- In this state FIFO is written with the
-- input stream data S_AXIS_TDATA
signal axis_tready : std_logic;
-- State variable
signal mst_exec_state : state;
-- FIFO implementation signals
signal byte_index : integer;
-- FIFO write enable
signal fifo_wren : std_logic;
-- FIFO full flag
signal fifo_full_flag : std_logic;
-- FIFO write pointer
signal write_pointer : integer range 0 to bit_num-1 ;
-- sink has accepted all the streaming data and stored in FIFO
signal writes_done : std_logic;
type BYTE_FIFO_TYPE is array (0 to (NUMBER_OF_INPUT_WORDS-1)) of std_logic_vector(((C_S_AXIS_TDATA_WIDTH/4)-1)downto 0);
begin
-- I/O Connections assignments
S_AXIS_TREADY <= axis_tready;
-- Control state machine implementation
process(S_AXIS_ACLK)
begin
if (rising_edge (S_AXIS_ACLK)) then
if(S_AXIS_ARESETN = '0') then
-- Synchronous reset (active low)
mst_exec_state <= IDLE;
else
case (mst_exec_state) is
when IDLE =>
-- The sink starts accepting tdata when
-- there tvalid is asserted to mark the
-- presence of valid streaming data
if (S_AXIS_TVALID = '1')then
mst_exec_state <= WRITE_FIFO;
else
mst_exec_state <= IDLE;
end if;
when WRITE_FIFO =>
-- When the sink has accepted all the streaming input data,
-- the interface swiches functionality to a streaming master
if (writes_done = '1') then
mst_exec_state <= IDLE;
else
-- The sink accepts and stores tdata
-- into FIFO
mst_exec_state <= WRITE_FIFO;
end if;
when others =>
mst_exec_state <= IDLE;
end case;
end if;
end if;
end process;
-- AXI Streaming Sink
--
-- The example design sink is always ready to accept the S_AXIS_TDATA until
-- the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words.
axis_tready <= '1' when ((mst_exec_state = WRITE_FIFO) and (write_pointer <= NUMBER_OF_INPUT_WORDS-1)) else '0';
process(S_AXIS_ACLK)
begin
if (rising_edge (S_AXIS_ACLK)) then
if(S_AXIS_ARESETN = '0') then
write_pointer <= 0;
writes_done <= '0';
else
if (write_pointer <= NUMBER_OF_INPUT_WORDS-1) then
if (fifo_wren = '1') then
-- write pointer is incremented after every write to the FIFO
-- when FIFO write signal is enabled.
write_pointer <= write_pointer + 1;
writes_done <= '0';
end if;
if ((write_pointer = NUMBER_OF_INPUT_WORDS-1) or S_AXIS_TLAST = '1') then
-- reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data
-- has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage).
writes_done <= '1';
end if;
end if;
end if;
end if;
end process;
-- FIFO write enable generation
fifo_wren <= S_AXIS_TVALID and axis_tready;
-- FIFO Implementation
--FIFO_GEN: for byte_index in 0 to (C_S_AXIS_TDATA_WIDTH/8-1) generate
--signal stream_data_fifo : BYTE_FIFO_TYPE;
--begin
-- Streaming input data is stored in FIFO
process(S_AXIS_ACLK)
begin
if (rising_edge (S_AXIS_ACLK)) then
if (S_AXIS_ARESETN = '0') then
start <= '0';
stop <= '0';
elsif (fifo_wren = '1') then
start <= S_AXIS_TDATA(1);
stop <= S_AXIS_TDATA(0);
else
start <= '0';
stop <= '0';
end if;
end if;
end process;
--end generate FIFO_GEN;
-- Add user logic here
-- User logic ends
end arch_imp;
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
set C_S00_AXIS_TDATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXIS_TDATA_WIDTH" -parent ${Page_0} -widget comboBox]
set_property tooltip {AXI4Stream sink: Data Width} ${C_S00_AXIS_TDATA_WIDTH}
}
proc update_PARAM_VALUE.C_S00_AXIS_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TDATA_WIDTH } {
# Procedure called to update C_S00_AXIS_TDATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXIS_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TDATA_WIDTH } {
# Procedure called to validate C_S00_AXIS_TDATA_WIDTH
return true
}
proc update_MODELPARAM_VALUE.C_S00_AXIS_TDATA_WIDTH { MODELPARAM_VALUE.C_S00_AXIS_TDATA_WIDTH PARAM_VALUE.C_S00_AXIS_TDATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXIS_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXIS_TDATA_WIDTH}
}
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
set C_S00_AXIS_TDATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXIS_TDATA_WIDTH" -parent ${Page_0} -widget comboBox]
set_property tooltip {AXI4Stream sink: Data Width} ${C_S00_AXIS_TDATA_WIDTH}
}
proc update_PARAM_VALUE.C_S00_AXIS_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TDATA_WIDTH } {
# Procedure called to update C_S00_AXIS_TDATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXIS_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TDATA_WIDTH } {
# Procedure called to validate C_S00_AXIS_TDATA_WIDTH
return true
}
proc update_MODELPARAM_VALUE.C_S00_AXIS_TDATA_WIDTH { MODELPARAM_VALUE.C_S00_AXIS_TDATA_WIDTH PARAM_VALUE.C_S00_AXIS_TDATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXIS_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXIS_TDATA_WIDTH}
}
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library ieee;
use ieee.std_logic_1164.all;
library work;
use work.types.all;
entity TB_TMC is
end TB_TMC;
architecture Behavioral of tb_tmc is
constant PERIOD : time := 10 ns;
signal clk : std_logic;
signal rst : std_logic;
signal one : std_logic := '1';
component TMC
generic (
numstarts : integer := 1;
numstops : integer := 1
);
port (
sysclk : in std_logic;
sysnrst : in std_logic;
starts : in std_logic_vector((numstarts - 1) downto 0);
stops : in std_logic_vector((numstops - 1) downto 0);
trigger : out std_logic;
errors : out std_logic_vector(1 downto 0); -- [Protocol Error (tmbxin.error), Double Start Error]
ready : in std_logic
);
end component;
signal trigger : std_logic;
signal errors : std_logic_vector(1 downto 0);
signal test : integer;
signal starts : std_logic_vector(3 downto 0);
signal stops : std_logic_vector(3 downto 0);
begin
DUT : tmc
generic map(
numstarts => 4,
numstops => 4
)
port map(
sysclk => clk,
sysnrst => rst,
starts => starts,
stops => stops,
trigger => trigger,
errors => errors,
ready => one -- be always ready
);
--generic map ( numinputs => 4)
--tmbin => (tmb0in, tmb1in, tmb2in, tmb3in),
CLOCK : process
begin
clk <= '1';
wait for PERIOD / 2;
clk <= '0';
wait for PERIOD / 2;
end process;
SIMULATION : process
begin
test <= 1; -- reset
starts <= "0000";
stops <= "0000";
rst <= '0';
wait for PERIOD * 2;
rst <= '1';
wait for PERIOD * 1;
test <= 0; -- WAITING
wait for PERIOD * 20;
test <= 2; -- bug-case
-- Start 1
starts <= "0001";
stops <= "0000";
wait for PERIOD * 1;
starts <= "0000";
stops <= "0000";
wait for PERIOD * 5;
-- Start 2
starts <= "0001";
stops <= "0000";
wait for PERIOD * 1;
starts <= "0000";
stops <= "0000";
wait for PERIOD * 5;
-- Stop 1
starts <= "0000";
stops <= "0010";
wait for PERIOD * 1;
starts <= "0000";
stops <= "0000";
wait for PERIOD * 5;
-- Start 3
starts <= "0001";
stops <= "0000";
wait for PERIOD * 1;
starts <= "0000";
stops <= "0000";
wait for PERIOD * 5;
-- Stop 2
starts <= "0000";
stops <= "0010";
wait for PERIOD * 1;
starts <= "0000";
stops <= "0000";
wait for PERIOD * 5;
-- Start 4
starts <= "0001";
stops <= "0000";
wait for PERIOD * 1;
starts <= "0000";
stops <= "0000";
wait for PERIOD * 5;
-- Stop 3
starts <= "0000";
stops <= "0010";
wait for PERIOD * 1;
starts <= "0000";
stops <= "0000";
wait for PERIOD * 5;
test <= 0; -- WAITING
wait for PERIOD * 10;
test <= 1; -- reset
starts <= "0000";
stops <= "0000";
rst <= '0';
wait for PERIOD * 1;
rst <= '1';
wait for PERIOD * 1;
test <= 0; -- WAITING
wait for PERIOD * 5;
test <= 3; -- measure 10 clk
-- Start
starts <= "0001";
stops <= "0000";
wait for PERIOD * 1;
starts <= "0000";
stops <= "0000";